1. Field of the Invention
The invention generally relates to a switching array and method for reducing ground current in busses. More particularly, this invention relates to a switching array and method in which switches are used in digital circuits, such as address or data busses, and are switched at different times thereby reducing the ground current that must be absorbed by a ground plane at any given instant of time.
2. Description of the Prior Art
In the field of digital computer circuits, which includes memory caches, memory arrays, graphics systems, video systems, imaging systems, and the like, it is common practice to use high speed switching circuits in connection with address or data busses. For instance, with reference to FIG. 1, an array 1 of switches 10 is shown with each switch 10.sub.i having its own input 12.sub.i and its own output 14.sub.i. The array 1 may have any number of switches 10 but normally will have multiples of 8, such as 8, 16, 32, 64, 128, etc.
While the switches 10 have their unique input 12 and output 14, the switches 10 share a common control line 16. The switches 10 latch the outputs 14 to the values of the voltages on their inputs at the time when a control signal is received on the control line 16. The number of switches 10 in the array 1 corresponds to the number of bits in the address or data bus. Thus, for many applications where the address or data buss is rather large, such as 64 bits or larger, the array 1 will have a corresponding large number of switches 10.
The outputs 14 of the switches 10 are digital signals with a logical value of "1" being represented by a high voltage at or near the Vcc supply and a logical value of "0" being represented by a "low" voltage at or near ground potential. When the output 14 of a switch 10 undergoes a transition from low to high, namely from a "0" to a "1," a capacitance associated with the output 14 must be charged to the Vcc supply voltage. On the other hand, when the output 14 of a switch 10 undergoes a transition from high to low, which is from "1" to "0," the charge on the output 14 must be discharged to ground in order to reduce the voltage from the "high" voltage to the "low" voltage.
The transition from a "1" to a "0" in a plurality of the switches 10 may produce problems in other circuitry. For example, a 64 bit array 1 of switches 10 may be associated with a graphics controller for displaying images on a computer monitor. When the image on the monitor changes from all black to all white, all of the outputs 14 of the switches 10 will change from high to low. Consequently, since all of the switches 10 discharge simultaneously, a maximum amount of current flows to ground and must be absorbed by a ground plane. As known to those skilled in the art, the current flowing to ground plane often increases the ground voltage due to the di/dt and IR effects. The increase in ground voltage, in turn, can alter the logic in other circuitry in the general vicinity, thereby resulting in a malfunction, "glitch," lock-up, or crash in the other circuitry. The problems in other circuitry may occur when less than all of the switches 10 undergo a transition from "1" to "0," such as with just a majority or substantial number of the switches 10.
Thus, it can be understood that when all or a significant plurality of the switches 10 in an array 1 are switched from high to low at the same time, the ground plane may be unable to absorb all of the current, thereby causing the difficulties generally discussed above.
Integrated chip (IC) manufacturers have addressed these problems by having "controlled edge rate" switching in the switches. The "controlled edge rate" switching reduces the inductive effects of the "di/dt" curve, which is the rate of change of current per unit time, and therefore reduces the amount of current flowing to the ground plane. While "controlled edge rate" switching has, to some extent, alleviated the above-mentioned problem, the problem has often become more aggravated since circuit designers are encouraged to use even more switches in an array.
Thus, it continues to be a problem in the art, especially as bit transfer rates increase and the size of busses increase, to address and overcome the problems raised when a significant number or all of the switches in an array simultaneously undergo a transition from high to low.